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1 ? fn3607.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved HFA1212 dual 350mhz, low power closed loop buffer amplifier the HFA1212 is a dual closed loop buffer featuring user programmable gain and high speed performance. manufactured on intersil?s proprietary complementary bipolar uhf-1 process, these devices offer wide -3db bandwidth of 350mhz, very fast slew rate, excellent gain flatness and high output current. a unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components. gain select ion is accomplished via connections to the inputs, as described in the ?application information? section. the result is a more flexible product, fewer part types in inventory, and more efficient use of board space. compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. unlike most buffers, t he standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. features ? differential gain . . . . . . . . . . . . . . . . . . . . . . . . . . 0.025% ? differential phase . . . . . . . . . . . . . . . . . . . . . 0.03 degrees ? wide -3db bandwidth (a v = +2). . . . . . . . . . . . . . 350mhz ? very fast slew rate (a v = -1) . . . . . . . . . . . . . . 1100v/ s ? low supply current . . . . . . . . . . . . . . . . . . . . 6ma/buffer ? high output current . . . . . . . . . . . . . . . . . . . . . . . . . 60ma ? excellent gain accuracy . . . . . . . . . . . . . . . . . . . 0.99v/v ? user programmable for closed-loop gains of +1, -1 or +2 without use of external resistors ? overdrive recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns ? standard operational amplifier pinout applications ? high resolution monitors ? professional video processing ? medical imaging ? video digitizing boards/systems ? rf/if processors ? battery powered communications ? flash converter drivers ? high speed pulse amplifiers pinout HFA1212 (soic) top view ordering information part number (brand) temp. range ( o c) package pkg. no. HFA1212ib (h1212i) -40 to 85 8 ld soic m8.15 out1 -in1 +in1 v- 1 2 3 4 8 7 6 5 v+ out2 -in2 +in2 - + - + data sheet august 2002
2 absolute maximum rati ng thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply output current (note 1) . . . . . . . . . . . . . . . . . short circuit protected esd rating human body model (per mil-std-883 method 3015.7) . . . .600v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 2) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature (die) . . . . . . . . . . . . . . . . . . . .175 o c maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. output is protected for short circuits to ground. brief shor t circuits to ground will not degrade reliability, however, conti nuous (100% duty cycle) output current should not exceed 30ma for maximum reliability. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications v supply = 5v, a v = +1, r l = 100 ?, unless otherwise specified. parameter test conditions (note 3) test level temp ( o c) min typ max units input characteristics output offset voltage a 25 - 2 10 mv afull- 315 mv average output offset voltage drift b full - 22 70 v/ o c channel-to-channel output offset voltage mismatch a 25 - - 15 mv afull- - 30 mv common-mode rejection ratio ? v cm = 1.8v a 25 42 45 - db ? v cm = 1.8v a 85 40 44 - db ? v cm = 1.2v a -40 40 45 - db power supply rejection ratio ? v ps = 1.8v a 25 45 49 - db ? v ps = 1.8v a 85 43 48 - db ? v ps = 1.2v a -40 43 48 - db input bias current a 25 - 1 15 a afull- 325 a input bias current drift b full - 30 80 na/ o c channel-to-channel input bias current mismatch a 25 - - 15 a afull- - 25 a input bias current power supply sensitivity ? v ps = 1.25v a 25 - 0.5 1 a/v afull- - 3 a/v input resistance ? v cm = 1.8v a 25 0.8 1.1 - m ? ? v cm = 1.8v a 85 0.5 1.4 - m ? ? v cm = 1.2v a -40 0.5 1.3 - m ? inverting input resistance c 25 - 350 - ? input capacitance c 25 - 2 - pf input voltage common mode range (implied by v io cmrr and +r in tests) a 25, 85 1.8 2.4 - v a-40 1.2 1.7 - v input noise voltage density (note 4) f = 100khz b 25 - 7 - nv/ hz input noise current density (note 4) f = 100khz b 25 - 3.6 - pa/ hz HFA1212
3 transfer characteristics gain (v in = -1v to +1v) a v = -1 a 25 -0.98 0.996 -1.02 v/v a full 0.975 1.000 -1.025 v/v a v = +1 a 25 0.98 0.992 1.02 v/v a full 0.975 0.993 1.025 v/v a v = +2 a 25 1.96 1.988 2.04 v/v a full 1.95 1.990 2.05 v/v channel-to-channel gain mismatch a v = -1 a 25 - - 0.02 v/v afull- - 0.025 v/v a v = +1 a 25 - - 0.025 v/v afull- - 0.025 v/v a v = +2 a 25 - - 0.04 v/v afull- - 0.05 v/v ac characteristics -3db bandwidth (v out = 0.2v p-p , note 4) a v = -1 b 25 - 300 - mhz a v = +1, +r s = 620 ? b 25 - 240 - mhz a v = +2 b 25 - 350 - mhz full power bandwidth (v out = 5v p-p at a v = +2 or -1, v out = 4v p-p at a v = +1, note 4) a v = -1 b 25 - 165 - mhz a v = +1, +r s = 620 ? b 25 - 150 - mhz a v = +2 b 25 - 125 - mhz gain flatness (v out = 0.2v p-p , note 4) a v = +2, to 25mhz b 25 - 0.03 - db a v = +2, to 50mhz b 25 - 0.04 - db crosstalk (all channels hostile, note 4) 5mhz b 25 - -65 - db 10mhz b 25 - -60 - db output characteristics output voltage swing (note 4) a v = -1 a 25 3.0 3.2 - v afull 2.8 3.0 - v output current (note 4) a v = -1, r l = 50 ? a 25, 85 50 55 - ma a -402842 - ma output short circuit current b 25 - 100 - ma dc closed loop output impedance a v = +2 b 25 - 0.2 - ? second harmonic distortion (a v =+2, v out =2v p-p , note 4) 10mhz b 25 - -60 - dbc 20mhz b 25 - -50 - dbc third harmonic distortion (a v =+2, v out =2v p-p , note 4) 10mhz b 25 - -60 - dbc 20mhz b 25 - -50 - dbc reverse isolation (s 12 , note 4) 30mhz, a v = +2 b 25 - -65 - db transient response a v = +2, unless otherwise specified rise and fall times (v out =0.5v p-p ) rise time b 25 - 1.0 - ns fall time b 25 - 1.1 - ns electrical specifications v supply = 5v, a v = +1, r l = 100 ?, unless otherwise specified. (continued) parameter test conditions (note 3) test level temp ( o c) min typ max units HFA1212
4 application information HFA1212 advantages the HFA1212 features a novel design which allows the user to select from three closed loop gains, without any external components. the result is a more flexible product, fewer part types in inventory, and more efficient use of board space. implementing a dual, gain of 2, cable driver with this ic eliminates the four gain setting resistors, which frees up board space for termination resistors. like most newer high performanc e amplifiers, the HFA1212 is a current feedback amplifier (cfa). cfas offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). the HFA1212 eliminates these concerns by br inging the gain setting resistors on-chip. this yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. because there is no access to the summing node, the pcb parasitics do not im pact performance at gains of +2 or -1 (see ?unity gain considerations? for discussion of parasitic impact on unity gain performance). the HFA1212?s closed loop gain implementation provides better gain accuracy, lower of fset and output impedance, and better distortion compared with open loop buffers. closed loop gain selection this ?buffer? operates in closed loop gains of -1, +1, or +2, with gain selection accomplished via connections to the inputs. applying the input signal to +in and floating -in selects a gain of +1 (see next section for layout caveats), while grounding -in selects a gain of +2. a gain of -1 is obtained by applying the input signal to -in with +in grounded through a 50 ? resistor. the table below summarizes these connections: overshoot (v out =0.5v p-p , v in t rise = 1ns, note 5) +os b 25 - 4 - % -os b 25 - 13 - % slew rate (v out = 5v p-p at a v = +2 or -1, v out = 4v p-p at a v = +1) a v = -1 +sr b 25 - 2000 - v/ s -sr b 25 - 1150 - v/ s a v =+1, +r s = 620 ? +sr b 25 - 1100 - v/ s -sr b 25 - 850 - v/ s a v = +2 +sr b 25 - 1300 - v/ s -sr b 25 - 900 - v/ s settling time (v out = +2v to 0v step, note 4) to 0.1% b 25 - 24 - ns to 0.05% b 25 - 37 - ns to 0.02% b 25 - 60 - ns overdrive recovery time v in = 2v b 25 - 8.5 - ns video characteristics differential gain (f = 3.58mhz, a v = +2) r l = 150 ? b 25 - 0.025 - % differential phase (f = 3.58mhz, a v = +2) r l = 150 ? b 25 - 0.03 - degrees power supply characteristics power supply range c 25 4.5 - 5.5 v power supply current a 25 - 5.9 6.1 ma/op amp a full - 6.1 6.3 ma/op amp note: 3. test level: a. production tested; b. typical or guaranteed limit based on characterization; c. design typical for information only. 4. see typical performance curves for more information. 5. negative overshoot dominates for output signal swings below gnd (e.g. 0.5v p-p ), yielding a higher overshoot limit compared to the v out = 0v to 0.5v condition. see the ?applic ation information? section for details. electrical specifications v supply = 5v, a v = +1, r l = 100 ?, unless otherwise specified. (continued) parameter test conditions (note 3) test level temp ( o c) min typ max units gain (a cl ) connections +input -input -1 50 ? to gnd input +1 input nc (floating) +2 input gnd HFA1212
5 unity gain considerations unity gain selection is accompli shed by floating the -input of the HFA1212. anything that tend s to short the -input to gnd, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. the result is excessive high frequency peaking, and possible instability. even the minimal amount of capacitance associated with attaching the -input lead to the pcb results in approximately 6db of gain peaking. at a minimum this requires due care to ensure the minimum capacitance at the -input connection. table 1 lists five alternate methods for configuring the HFA1212 as a unity gain buffer, and the corresponding performance. the implementations vary in complexity and involve performance trade-offs. the easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. the amplifier bandwidth decreases from 430mhz to 280mhz, but excellent gain flatness is the benefit. a drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. alternately, a 100pf capacitor between the inputs shorts them only at high frequencies, which prevents the increased output offset voltage but delivers less gain flatness. another straightforward approach is to add a 620w resistor in series with the amplifier?s positive input. this resistor and the HFA1212 input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. this configuration was employed to obtain the data sheet ac and transient parameters for a gain of +1. pulse overshoot the HFA1212 utilizes a quasi- complementary output stage to achieve high output current while minimizing quiescent supply current. in this approach, a composite device replaces the traditional pnp pulldown transistor. the composite device switches modes after crossing 0v, resulting in added distortion for signals swinging below ground, and an increased overshoot on the negative portion of the output waveform (see figure 6, figure 9, and figure 12). this overshoot isn?t present for small bipolar signals (see figure 4, figure 7, and figure 10) or large positive signals (see figure 5, figure 8 and figure 11). pc board layout this amplifier?s frequency re sponse depends greatly on the care taken in designing the pc board (pcb). the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value (0.1 f) chip capacitor wor ks well in most cases. terminated microstrip signal lines are recommended at the input and output of the device . capacitance directly on the output must be minimized, or isolated as discussed in the next section. an example of a good high frequency layout is the evaluation board shown in figure 3. driving capacitive loads capacitive loads, such as an a/d input, or an improperly terminated transmission line will degrade the amplifier?s phase margin resulting in frequency response peaking and possible oscillations. in most cases, the oscillation can be avoided by placing a resistor (r s ) in series with the output prior to the capacitance. figure 1 details starting points for the selection of this resistor. the points on the curve indicate the r s and c l combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. r s and c l form a low pass network at the output, thus limiting system bandwidth well bel ow the amplifier bandwidth of 350mhz. by decreasing r s as c l increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. in spite of this, bandwidth decreases as the load capacitance increases. table 1. unity gain performance for various implementations approach peaking (db) bw (mhz) 0.1db gain flatness (mhz) remove -in pin 4.5 430 21 +r s = 620 ? 0 220 27 +r s = 620 ? and remove -in pin 0.5 215 15 short +in to -in (e.g., pins 2 and 3) 0.6 280 70 100pf capacitor between +in and -in 0.7 290 40 HFA1212
6 evaluation board the performance of the HFA1212 may be evaluated using the ha5023 evaluation board, sl ightly modified as follows: 1. remove the two feedback resistors, and leave the con- nections open. 2. a. for a v = +1 evaluation, remove the gain setting resistors (r 1 ), and leave pins 2 and 6 floating. b. for a v = +2, replace the gain setting resistors (r 1 ) with 0 ? resistors to gnd. 3. replace the 0 ? series output resistors with 50 ? . the modified schematic for amplif ier 1, and the board layout are shown in figures 2 and 3. note: note: the soic version may be evaluated in the dip board by using a soic-to-dip adapter su ch as aries electronics part number 08-350000-10. to order evaluation boards (part number ha5023eval), please contact your local sales office. 0 100 200 300 400 0 10 20 30 40 50 load capacitance (pf) series output resistance ( ? ) a v =+2 150 250 350 50 a v =+1 figure 1. recommended series resistor vs load capacitance ? 5v 10 f0.1 f 50 ? gnd gnd r 1 + 5 v 0.1 f 10 f 50 ? in out (a v = + 1) or 0 ? (a v = + 2) note: r 1 = + ? (note) 1 2 3 4 8 7 6 5 figure 2. modified evaluation board schematic figure 3a. top layout figure 3b. bottom layout figure 3. evaluation board layout HFA1212
7 typical performance curves v supply = 5v, t a = 25 o c, r l = 100 ?, unless otherwise specified figure 4. small signal pulse response figure 5. large signal positive pulse response figure 6. large signal bipolar pulse respo nse figure 7. small signal pulse response figure 8. large signal positi ve pulse response figure 9. large signal bipolar pulse response time (5ns/div.) output voltage (mv) 200 150 100 50 0 -50 -100 -150 -200 a v = + 2 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = + 2 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = + 2 time (5ns/div.) output voltage (mv) 200 150 100 50 0 -50 -100 -150 -200 a v = + 1 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = + 1 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = + 1 HFA1212
8 figure 10. small signal pulse response figur e 11. large signal positive pulse response figure 12. large signal bipolar pul se response figure 13. frequency response figure 14. full power bandwidth figure 15. gain flatness typical performance curves (continued) v supply = 5v, t a = 25 o c, r l = 100 ?, unless otherwise specified time (5ns/div.) output voltage (mv) 200 150 100 50 0 -50 -100 -150 -200 a v = -1 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = ? 1 time (5ns/div.) output voltage (v) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 a v = -1 phase gain 1 10 100 600 frequency (mhz) 6 3 0 -3 -6 -9 normalized gain (db) a v = -1 a v = +1 a v = +2 a v = +1 a v = +2 -90 -180 -270 -360 0 normalized phase (degrees) v out = 200mv p-p + r s = 620 ? ( + 1) + r s = 0 ? (-1, +2) v out = 4v p-p (+1) v out = 5v p-p (-1, +2) + r s = 620 ? (+1) 6 3 0 -3 -6 -9 1 10 100 300 frequency (mhz) normalized gain (db) a v = -1 a v = +2 a v = +1 1 10 100 frequency (mhz) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 normalized gain (db) v out = 200mv p-p + r s = 620 ? ( + 1) + r s = 0 ? (-1, +2) a v = + 1 a v = -1 a v = + 2 HFA1212
9 figure 16. reverse isolation f igure 17. all hostile crosstalk figure 18. 2nd harmonic distortion vs p out figure 19. 3rd harmonic distortion vs p out figure 20. settling response figure 21. input noise characteristics typical performance curves (continued) v supply = 5v, t a = 25 o c, r l = 100 ?, unless otherwise specified 0.3 1 10 100 frequency (mhz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 gain (db) a v = -1 a v = + 1 a v = + 2 0.3 1 10 100 500 frequency (mhz) -110 -100 -90 -10 -20 -80 -70 -30 -40 -50 -60 crosstalk (db) a v = + 2 r l = r l = 100 ? -40 15 output power (dbm) distortion (dbc) -10 -5 0 5 10 -70 -65 -60 -55 -50 -45 20mhz 10mhz -10 -5 0 5 10 15 -70 -65 -60 -55 -50 -45 -40 output power (dbm) distortion (dbc) 20mhz 10mhz 13 33 53 73 93 113 153 173 133 time (ns) 0.10 0.05 0 -0.05 -0.10 settling error (%) a v = +1 20 16 12 8 4 20 16 12 8 4 0 0.1 1 10 100 frequency (khz) noise voltage (nv/ hz ) 0 noise current (pa/ hz ) e ni i ni HFA1212
10 die characteristics die dimensions: 69 mils x 92 mils x 19 mils 1750 m x 2330 m x 483 m metallization: type: metal 1: aicu(2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: aicu(2%) thickness: metal 2: 16k ? 0.8k ? passivation: type: nitride thickness: 4k ? 0.5k ? transistor count: 180 substrate potential (powered up): floating (recommend connection to v-) figure 22. output voltage vs temperature typical performance curves (continued) v supply = 5v, t a = 25 o c, r l = 100 ?, unless otherwise specified 3.6 3.5 3.4 3.3 3.2 3.1 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 temperature ( o c) output voltage (v) 3.0 + v out (r l = 50 ?) |-v out | (r l = 50 ? ) +v out (r l = 100 ? ) |-v out | (r l = 100 ?) a v = -1 HFA1212
11 metallization mask layout nc +in1 -in1 v+ out1 nc -in2 out2 nc nc +in2 nc nc HFA1212 v- HFA1212
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HFA1212 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93

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